ARM and Cadence Optimize Digital SoC Design Through Expanded Collaboration; Alliance Produces Methodology Kit to Improve Performance, Power, and Area for Synthesizable ARM Processors
SANTA CLARA, Calif. & CAMBRIDGE, United Kingdom—(BUSINESS WIRE)—Sept. 12, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN)
and ARM (LSE:ARM) (Nasdaq:ARMHY) today announced they have extended
their design chain alliance to deliver further benefits to their
mutual customers. This phase builds on the companies' existing
collaborations on digital IC design, power management and verification
to provide new solutions for application-specific needs. The result is
the Cadence(R) Optimization Methodology Kit for ARM(R) Processors,
which helps design teams enhance performance, power utilization, and
area when hardening synthesizable ARM processors.
The goal of the Cadence Kits approach is to simplify the
application of Cadence technology and so shorten time-to-productivity.
Customers can then focus their precious design resources on design
differentiation rather than design infrastructure. Cadence Kits
address application-specific design challenges by combining a verified
methodology, packaged in platform flows, with IP and consulting all
demonstrated on a representative reference design.
The Cadence Optimization Methodology Kit for ARM Processors builds
on the success of the silicon-proven ARM-Cadence Encounter(R)
Reference Methodology. In addition to the reference methodology, the
kit includes Cadence Encounter RTL Compiler synthesis, First
Encounter(R) silicon virtual prototyping, front-end views for the ARM
Artisan(R) SAGE-X(TM) standard cell libraries for TSMC's 0.13-micron
and 90-nanometer G processes, and service and support to help
designers achieve high performance, low power and small area levels,
while reducing development time.
As two founding members of the Silicon Design Chain Initiative,
ARM and Cadence have collaborated on solutions to reduce risks and
design time for their customers. For example, the companies have
already delivered:
-- Low-power design techniques demonstrated to reduce power by
more than 40 percent on a 90-nanometer test design.
-- Accelerated SoC emulation by integrating the Cadence
Incisive(R) functional verification platform and the ARM
Integrator(TM) Logic Tile products.
-- The ARM-Cadence Reference Methodology, which enables
predictable performance, power and area results.
"Today's disaggregated design chain requires a more integrated,
collaborative approach to massively simplify the design process," said
Jan Willis, senior vice president of Industry Alliances at Cadence.
"This Methodology Kit leverages expertise from both companies to help
our customers rapidly reach the target frequency, die size, and power
consumption requirements for their particular markets."
"At Oki, we have seen substantial power and area savings using
Encounter RTL Compiler on our designs based on our uPLAT SoC System
LSI Design Platform, which features the ARM946E-S(TM) processor," said
Masakazu Urahama, manager of the Silicon Platform Design Department,
LSI Design Division, at Oki Electric Industry Co., Ltd. "We are
excited to see Cadence and ARM working together to deliver further
benefits in a streamlined flow with the Cadence Optimization
Methodology Kit for ARM Processors."
"ARM and Cadence originally developed the ARM-Cadence Reference
Methodology to provide excellent support for our mutual customers,"
said Mike Inglis, executive vice president of Marketing at ARM. "As
the complexity of design tasks has increased with lower-power and
higher-performance requirements, we have increased our level of
integration and validation with Cadence through efforts such as the
Silicon Design Chain Initiative. The new Methodology Kit builds on
this collaboration by providing the technology, support and training
necessary to enable our Partners to achieve their specific power,
performance and area goals in hardening synthesizable ARM processors."
This deepening relationship between ARM and Cadence will result in
additional projects to ensure more optimized products from both
companies are aligned to meet customer market requirements. Areas of
collaboration include extending the companies' continuing work in
advanced processor cores, system verification, and on extending the
effective current source delay model (ECSM) which Cadence pioneered.
The companies will expand work done through the Silicon Design Chain
Initiative to add additional low-power design capabilities, and also
extend support for system languages, including the e, SystemC, and
SystemVerilog languages.
Availability
The Cadence Optimization Methodology Kit for ARM Processors will
be available in October 2005. More information can be found at
http://www.cadence.com/datasheets/armopt_ds.pdf.
About ARM
ARM designs the technology that lies at the heart of advanced
digital products, from wireless, networking and consumer entertainment
solutions to imaging, automotive, security and storage devices. ARM's
comprehensive product offering includes 16/32-bit RISC
microprocessors, data engines, 3D processors, digital libraries,
embedded memories, peripherals, software and development tools, as
well as analog functions and high-speed connectivity products.
Combined with the company's broad Partner community, they provide a
total system solution that offers a fast, reliable path to market for
leading electronics companies. More information on ARM is available at
http://www.arm.com.
About Cadence
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, printed circuit boards and systems used in consumer
electronics, networking and telecommunications equipment, and computer
systems. Cadence reported 2004 revenues of approximately $1.2 billion,
and has approximately 5,000 employees. The company is headquartered in
San Jose, Calif., with sales offices, design centers, and research
facilities around the world to serve the global electronics industry.
More information about the company, its products, and services is
available at www.cadence.com.
Cadence, the Cadence logo, Encounter, First Encounter and Incisive
are registered trademarks of Cadence Design Systems, Inc.
ARM is a registered trademark of ARM Limited. ARM946E-S, ARM11,
Integrator and SAGE are trademarks of ARM Limited. Artisan Components
and Artisan are registered trademarks and SAGE-X is a trademark of ARM
Physical IP, Inc., a wholly owned subsidiary of ARM. "ARM" is used to
represent ARM Holdings plc; its operating company ARM Limited; and the
regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan;
ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.;
AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Technologies Pvt.
Ltd.; and ARM Physical IP, Inc.
Contact:
Cadence
Bruce Chan, 408-894-2961
Email Contact
or
ARM
Michelle Spencer, +44 1628 427780
Email Contact
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